3-bit Magnitude Comparator using logic gates

3-bit Magnitude Comparator using logic gates

A 3-bit comparator which is designed using logic gates E.g.  XNOR, OR, AND etc. 

The code was tested using  a test-bench code which tested the design for all the 81 combinations of inputs.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity comparator is
port( a,b : in unsigned(2 downto 0);  --3 bit numbers that are to be compared
        a_equal_b   : out std_logic;  --a is equal to b
        a_less_b    : out std_logic;  --a is less than b
        a_greater_b : out std_logic   --a is greater than b
      );    
end comparator;

architecture gate_level of comparator is

signal w1,w2,w3,w4,w5,w6,w7,w8,w9 : std_logic := '0';

BEGIN

w1 <= not(a(2) xor b(2));  --XNOR-gate with 2 inputs.
w2 <= not(a(1) xor b(1));  --XNOR-gate with 2 inputs.
w3 <= not(a(0) xor b(0));  --XNOR-gate with 2 inputs.
w4 <= (not a(2)) and b(2);
w5 <= (not a(1)) and b(1);
w6 <= (not a(0)) and b(0);
w7 <= a(2) and (not b(2));
w8 <= a(1) and (not b(1));
w9 <= a(0) and (not b(0));

a_equal_b <= w1 and w2 and w3;  --  a is equals to b.
a_less_b <= w4 or (w1 and w5) or (w1 and w2 and w6); -- a is less than b
a_greater_b <= w7 or (w1 and w8) or (w1 and w2 and w9); -- a is greater than b

end gate_level;

Test-bench code:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY t_b IS
END t_b;

ARCHITECTURE behavior OF t_b IS
   --Inputs
   signal a : unsigned(2 downto 0) := (others => '0');
   signal b : unsigned(2 downto 0) := (others => '0');
    --Outputs
   signal a_equal_b : std_logic;
   signal a_less_b : std_logic;
   signal a_greater_b : std_logic;

    signal x,y : integer;

BEGIN

   uut: entity work.comparator PORT MAP (
          a => a,
          b => b,
          a_equal_b => a_equal_b,
          a_less_b => a_less_b,
          a_greater_b => a_greater_b
        );

   stim_proc: process
   begin       
        for x in 0 to 8 loop
            for y in 0 to 8 loop
                a <= to_unsigned(x,3);
                b <= to_unsigned(y,3);
                wait for 10 ns;
            end loop;
        end loop;  
   end process;

END;

Verilog code for a comparator-VHDL

What is Comparator?

In Electronics, a comparator is used to compares two voltages (V) / Currents(I) and outputs a digital signal indicating which is larger than other. it consist of two analog input terminals ${\displaystyle {�}_{+}}$ and ${\displaystyle {�}_{-}}$ and one binary digital output ${\displaystyle {�}_{\text{o}}}$. The output is ideally as follows

A comparator mainly has a specialized high gain Differential amplifier. Comparators are commonly used in devices that measure and digitize two analog signals, for example analog to digital signals (ADCs), as well as oscillators.

Verilog code for a 2 bit -comparator-VHDL

There are many different types of comparators. But, Here we have designed and implemented a simple 2bit-comparator which has two 2 bit inputs and three output bits these outputs says, whether one of the input is less ,greater or equal to the second input.

A 2-bit comparator is a device that compares 2-binary numbers, each of two bits and produces as one number is equal(=) or greater than (>) or less than (<) the other.

A simple 2-bit Comparator device is designed and implemented in VHDL/ Verilog Code.

The 2-bit comparator specifications are as follows:

• Inputs: 2-bit A and B for comparison.
• Output:
• A>B: high if A > B else low
• A=B: high if A = B else low
• A<B: high if A<B else low
• The Truth bale for 2-bit Comparator is given Below 

K-map

Equations For 2-bit Comparator

Circuit Diagrams

This is the Verilog code for the 2bit-comparator:

 // Verilog code for 2-bit comparator   
 module 2bit-comparator(input [1:0] A,B, output A-equal-B, A-less-B, A-greater-B);  
 wire w0,w1,w2,w3,w4,w5,w6,w7;  
 // A equal B output   
 xnor x1(w0,A[1],B[1]);  
 xnor x2(w1,A[0],B[0]);  
 and x3(A-equal-B,w0,w1);  
 // A < B output   
 assign w2 = (~A[0])& (~A[1])& B[0];  
 assign w3 = (~A[1])& B[1];  
 assign w4 = (~A[0])& B[1]& B[0];  
 assign A-less-B = w2 | w3 | w4;  
 // A > B output   
 assign w5 = (~B[0])& (~B[1])& A[0];  
 assign w6 = (~B[1])& A[1];  
 assign w7 = (~B[0])& A[1]& A[0];  
 assign A-greater-B = w5 | w6 | w7;  
 endmodule   
 `timescale 10 ps/ 10 ps     
 // Verilog test-bench code for 2-bit comparator   
 module test_comparator;  
 reg [1:0] A, B;  
 wire A-less-B, A-equal-B, A-greater-B;  
 integer i;   
 comparator dutt(A,B,A-less-B, A-equal-B, A-greater-B);  
 initial begin  
      for (i=0;i<4;i=i+1)  
      begin   
           A = i;  
           B = i + 1;  
           #20;  
      end   
      for (i=0;i<4;i=i+1)  
      begin   
           A = i;  
           B = i;  
           #20;  
      end   
      for (i=0;i<4;i=i+1)  
      begin   
           A = i+1;  
           B = i;  
           #20;  
      end   
 end   
 endmodule

2 bit comparator logic diagram,