Parallel Multiplier Verilog HDL code

Verilog Code for Parallel Multiplier:

A parallel multiplier is a type of digital circuit that performs multiplication on two numbers in parallel, using multiple arithmetic units in parallel. This allows the circuit to perform multiplication faster than a serial multiplier, which performs multiplication using a single arithmetic unit.

fpga verilog code example

Code For Parallel Multiplier.

//parallel multiplier (n = 8)

module parallel_Multiplier (Product, multiplicand, Multiplier);

input [7: 0] multiplicand, Multiplier;

output reg [15: 0] Product;

always @ (multiplicand, Multiplier)

Product1 = multiplicand*Multiplier;

endmodule

module Algorithmic-Binary-Multiplier #(parameter dp-width =5) (

output [2*dp_width -1 : 0] Product, Input [dp-width -1 : 0] multiplicand, Multiplier);

reg [dp-width -1: 0] A, B, Q; //Sized for datapath

reg C;

Integer k;

assign Product1 = {C, A, Q};

always @ (multiplicand, Multiplier) begin

Q = Multiplier;

B = multiplicand;

C=0;

A=0;

for(k= 0; k <= dp-width-1; k= k+ 1)
begin

if (Q[0]) {(C, A) = A + B;

{C, A, Q) = {C, A, Q} >> 1;

end

end

endmodule

module t-Algorithmic-Binary-Multiplier;

parameter dp-width = 5; // Width of data path

wire [2* dp-width -1: 0] Prdct;

reg [dp-width -1: 0]multiplicand, Multiplier;

integer Exp-Value;

reg Error;

Algorithmic-Binary-Multiplier M0 (Product, multiplicand, Multiplier);

// Error detection

initial# 1030000 finish:

always @ (Product) begin

Exp-Value =multiplicand, Multiplier;

Error = Exp-Value ^ Product;

end

initial begin

#5 multiplicand= 0;

 Multiplier = 0;

repeat (32)# 10 begin  Multiplier =  Multiplier + 1;

repeat (32) #5 multiplicand= multiplicand + 1 :

end

end

endmodule

Here is an example of VHDL code for a parallel multiplier:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity parallel_multiplier is Port ( a : in STD_LOGIC_VECTOR (3 downto 0); b : in STD_LOGIC_VECTOR (3 downto 0); p : out STD_LOGIC_VECTOR (7 downto 0)); end parallel_multiplier; architecture Behavioral of parallel_multiplier is begin p <= a * b; end Behavioral;

This code defines a parallel multiplier module called "parallel_multiplier" with two inputs "a" and "b" and an output "p". The inputs are 4-bit vectors and the output is 8-bit vector. The architecture uses the built-in multiplication operator to perform the multiplication of the inputs in parallel.

Here is an example of Verilog code for a parallel multiplier:

module parallel_multiplier(input [3:0] a, input [3:0] b, output [7:0] p); assign p = a * b; endmodule

This code defines a parallel multiplier module called "parallel_multiplier" with two inputs "a" and "b" and an output "p". The inputs are 4-bit vectors and the output is 8-bit vector. The assign statement is used to perform the multiplication of the inputs in parallel.

Please note that this is a basic example and the actual code will depend on the specific requirements of your design, the width of the inputs, and the width of the output. Some designs may require more complex implementation and also this is a combinational multiplier and not a pipelined multiplier.

Transmission Gate Verilog code

Transmission Gate:

In VHDL the transmission gate is represented with the keyword Cmos. Transmission Gate has one output, one input and two control signals. It is referred to as a Cmos switch. The code for Transmission gate is as follows:
cmos (output, Input, contorl1, control2); // general description
cmos (Y, X, A, B); // transmission gate
Normally, control signal 1 and control signal 2 are the complement of each others. The Cmos switch doesn't need any power source, However VDD and ground are connected to the substrates of the MOS transistors. Tansmission gates are useful for building Multiplexer (MUX) and flip-flops with CMOS circuits.

                                                   Transmission Gate

                                                      Block diagram

                                                Behavior of the switch

fpga verilog code example

Verilog Code for Transmission gate : 

module Cmos-XOR (A, B, Y);
Input A, B;
output Y:
wire A1, B1;
// represented inverter
inverter in1 {A1, A);
inverter in2 (B1, B);
// instantiate Cmos switch
cmos (Y, B, A1, A);                 // cmos (output, Input, control1, control2);
cmos (Y, B1, A, A1);
endmodule

//Cmos Inverter
module inverter (Y, A);
input A;
output Y;
supply1 PWR;
supply0 GND;
pmos (Y, PWR, A);  //(Drain, source. gate)
nmos (Y, GND, A);
endmodule

// Stimulus to test Cmos-XOR
module test-Cmos-XOR;
reg A,B;
wire Y;
//instantiate Cmos-XOR
Cmos-XOR XI (A, B, Y);
// Apply truth table
initial
begin
A = I'b0; B = 1'b0;
#5 A = I'b0; B = l'bl;
#5A = I'bl; B = l'b0;
#5A = l'bl; B = l'bl;
end

// Display results
initial
$monitor ("A =%b B= %b Y =%b", A, B, Y);
endmodule