How to make 8x1 Multiplexer using 2 4x1 Multiplexer? as we know a multiplexer has 1 output and 2n where n is the no. of select lines. Following is the logic Diagrams for 8x1 Mux using two 4x1 Mux.
VHDL code of 8x1mux using two 4x1 Mux :
module 8x1_mux_using_2_4x1_mux{O,s,i);
input [7:0]i;
input[2:0]s;
output O;
mux a ({s[1:0]},{ i[3:0]},w1);
mux a1({s[1:0]},{ i[7:4]},w2);
not n(w3,s[2]);
and an(w4,w1,w3):
and an1(w5,w2,s[2]):
nor n1(o,w4,w5):
endmodule
module mux( sel, in, out );
input[1:0] sel;
input[3:0] in;
output out;
reg output;
always @( sel or in )
begin
if( sel == 0)
out = in[0];
else if( sel == 1)
out = in[1];
else if( sel == 2)
out = in[2];
else if( sel == 3)
out = in[3];
else
out=1’bX
end
endmodule
fpga verilog code example
This comment has been removed by the author.
ReplyDeletehi the above code is not perfect it is only for 1 bit per input.
ReplyDeletei have written code for 4 bit per input with testbench.
///////////////////////////////////////////////////////////
owner:Harshad Sarswa
Code: 8x1 mux using two 4x1
////////////////////code starts here//////////////////
module mux_8x1(
input [3:0] a,
input [3:0] b,
input [3:0] c,
input [3:0] d,
input [3:0] e,
input [3:0] f,
input [3:0] g,
input [3:0] h,
input [2:0] sel,
output [3:0] out
);
wire [3:0] w1,w2,w3,w4,w5;
mux mx1[3:0](a,b,c,d,sel[1:0],w1);
mux mx2[3:0](e,f,g,h,sel[1:0],w2);
not n1[3:0](w3,sel[2]);
and a1[3:0](w4,w1,w3);
and a2[3:0](w5,w2,sel[2]);
or o1[3:0](out,w4,w5);
endmodule
module mux(in1,in2,in3,in4,select,op);
input [3:0] in1;
input [3:0] in2;
input [3:0] in3;
input [3:0] in4;
input [1:0] select;
output reg [3:0] op;
always@(in1 or in2 or in3 or in4 or select) begin
case (select)
2'b00 : op <= in1;
2'b01 : op <= in2;
2'b10 : op <= in3;
2'b11 : op <= in4;
endcase
end
endmodule
//testench
module tb_8to1_mux;
reg [3:0] a;
reg [3:0] b;
reg [3:0] c;
reg [3:0] d;
reg [3:0] e;
reg [3:0] f;
reg [3:0] g;
reg [3:0] h;
reg [2:0] sel;
wire [3:0] out;
integer i;
mux_8x1 mux0(.a(a),.b(b),.c(c),.d (d),.e(e),.f(f),.g(g),.h(h),.sel(sel),.out(out));
initial begin
$dumpfile("muxx.vcd");
$dumpvars(0,tb_8to1_mux);
$monitor ("[%0t] sel=0x%0h a=0x%0h b=0x%0h c=0x%0h d=0x%0h e=0x%0h f=0x%0h g=0x%0h h=0x%0h out=0x%0h", $time, sel, a, b, c, d, e, f, g, h, out);
sel <= 0;
a <= $random;
b <= $random;
c <= $random;
d <= $random;
e <= $random;
f <= $random;
g <= $random;
h <= $random;
for (i = 0; i < 7; i=i+1) begin
#5 sel <= i;
end
#5 $finish;
end
endmodule