3- to-8 line Decoder full Block Diagram, Truth Table, and Logic Diagram

 What is  a Decoder:

         A decoder is used to convert binary into decimal. Decoder is a combinational logic circuit that has n input lines and a maximum of 2n unique output lines.

fpga verilog code example

3-to-8 Line Decoder:

               A 3x8 lines decoder has three inputs  i.e A,B,C and eight outputs i.e D0 ,D1,D2,D3,D4,D5,D6 and  D7. which are generated by using inputs i.e 2^3.

Block Diagram of 3X8 Decoder:

fig1. Block Diagram of 3X8 Decoder

Truth Table of 3X8 decoder:

fig2.Truth Table of 3X8 decoder

D0 = A’B’C’

D1= A’B’C

D2 = A’BC’

D3 = A’BC

D4 = AB’C’

D5= AB’C

D6 = ABC’

D7 = ABC

Logic Diagram of 3X8 Decoder:

fig3. Logic Diagram of 3X8 Decoder

D-Latch Verilog code:

The D-latch is a transparent and responds to a change in data input with a change in output, as long as
the enable input is high. It has one output Q and  two inputs, D and en. Since Q is evaluated in a procedural statement, it must be declared as register type. D-latch responds to input signal levels, so the two inputs are listed without edge qualifiers in the event enable expression following the @ symbol in the always statement. it has only one blocking procedural assignment statement and it also specifies the transfer of D-input to Q-output if logic 1 i.e when enable is true. This statement is executed every time when there is a change in input D if enable is  logic1.

D-Latch Gate level and truth Table.

D-Latch Graphical Symbol.

fpga verilog code example

Verilog of D latch
module D-latch (Q, 0, en); // en is enable
output Q;
Input D, en;
reg Q;
always @ (en or D)
If (en) Q <= D;   //Same as: If (enable == 1)
endmodule


// Alternative syntax 
module D-latch (output reg Q, input enable, D);
always @ (enable, D)
If (enable) Q <= D;   // No action if enable not asserted
endmodule

Here is an example of VHDL code for a D-latch:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity D_latch is Port ( D : in STD_LOGIC; clk : in STD_LOGIC; Q : out STD_LOGIC); end D_latch; architecture Behavioral of D_latch is begin process(clk) begin if (clk'event and clk = '1') then Q <= D; end if; end process; end Behavioral;

And here is an example of Verilog code for a D-latch:

module D_latch (input D, clk, output reg Q); always @(posedge clk) begin Q <= D; end endmodule

Both codes define a D-latch module with inputs D and clk, and an output Q. The D-latch is a level sensitive device and uses the input D as the data input, and the input clk as the enable input.

In the VHDL code, the process is sensitive to the clock input and the output Q is assigned the value of the input D when there is a rising edge on the clock input.

In the Verilog code, the always block is triggered on the rising edge of the clock input and assigns the value of the input D to the output Q.

Both codes implements the same functionality and are equivalent. Please note that this is a basic example and the actual code may depend on the specific requirements of your design.