Verilog Code for 4x1 mux

Multiplexer:

Multiplexers has 1 output and 2ⁿ Inputs,  where n is the number of select lines .Let suppose,  if we have 4 inputs like: in0, in1, in2, in3,in4,in5,in6 and in7 .Now we want any 1 input shown as it  to the output then it will based on the selection signals that are select lines. In the following table 3 bits select lines decide which input goes to output.

Verilog code of 4x1mux:

module _mux( sel, in, out );
input[1:0] sel;
input[3:0] in;
output out;
reg output;
always @( sel or in )
begin
if( sel == 0)
out = in[0];
else if( sel == 1)
out = in[1];
else if( sel == 2)
out = in[2];
else if( sel == 3)
out = in[3];
else
out=1’bX;
end
endmodule

fpga verilog code example