Transmission Gate Verilog code

Transmission Gate:

In VHDL the transmission gate is represented with the keyword Cmos. Transmission Gate has one output, one input and two control signals. It is referred to as a Cmos switch. The code for Transmission gate is as follows:
cmos (output, Input, contorl1, control2); // general description
cmos (Y, X, A, B); // transmission gate
Normally, control signal 1 and control signal 2 are the complement of each others. The Cmos switch doesn't need any power source, However VDD and ground are connected to the substrates of the MOS transistors. Tansmission gates are useful for building Multiplexer (MUX) and flip-flops with CMOS circuits.

                                                   Transmission Gate

                                                      Block diagram

                                                Behavior of the switch

fpga verilog code example

Verilog Code for Transmission gate : 

module Cmos-XOR (A, B, Y);
Input A, B;
output Y:
wire A1, B1;
// represented inverter
inverter in1 {A1, A);
inverter in2 (B1, B);
// instantiate Cmos switch
cmos (Y, B, A1, A);                 // cmos (output, Input, control1, control2);
cmos (Y, B1, A, A1);
endmodule

//Cmos Inverter
module inverter (Y, A);
input A;
output Y;
supply1 PWR;
supply0 GND;
pmos (Y, PWR, A);  //(Drain, source. gate)
nmos (Y, GND, A);
endmodule

// Stimulus to test Cmos-XOR
module test-Cmos-XOR;
reg A,B;
wire Y;
//instantiate Cmos-XOR
Cmos-XOR XI (A, B, Y);
// Apply truth table
initial
begin
A = I'b0; B = 1'b0;
#5 A = I'b0; B = l'bl;
#5A = I'bl; B = l'b0;
#5A = l'bl; B = l'bl;
end

// Display results
initial
$monitor ("A =%b B= %b Y =%b", A, B, Y);
endmodule