Verilog Code for Carry Look-ahead Adder

Carry Lookahead Adder:

A Carry lookahead adder is a very complex hardwareadder. In carry lookahead adder the ripple carry transformed in such that the carry logic is reduced to two-level logic. Following is the Verilog code for Carry LookAhead adder: 

fpga verilog code example

VHDL for Carry Lookahead Adder:

module carry_lookahead_addre(a,b, cin, s, cout , pg, gg);
input [3:0]a,b;
input cin;
output [3:0]s;
output cout,pg,gg;
wire [3:0]p,g,c;
assign g=a&b;
assign p=a^b;
assign c[0]=cin;
assign c[1]=g[0]|(p[0]&c[0]);
assign c[2]=g[1]|(p[1]&g[0])|(p[1]&p[0]&c[0]);
assign c[3]=g[2]|(p[2]&g[1])|(p[2]&p[1]&g[0])|(p[1]&p[2]&c[0]);
assign cout=g[3]|(p[3]&g[2])|(p[3]&p[2]&g[1])|(p[3]&p[2]&p[1]&g[0])|(p[3]&p[2]&p[1]&p[0]&c[0]);
assign sum=p^c;
assign pg=p[3]&p[2]&p[1]&p[0];
assign gg=g[3]|(p[3]&g[2])|(p[3]&p[2]&g[1])|(p[3]&p[2]&p[1]&g[0]);
endmodule

 TestBench for Carry Lookahead Adder;

module carry_v;
// Inputs
reg [3:0] a;
reg [3:0] b;
reg cin;
// Outputs
wire [3:0] s;
wire cout;
wire pg;
wire gg;
// Instantiate the Unit Under Test (UUT)
carrylookahead uut (
.a(a),
.b(b),
.cin(cin),
.s(s),
.cout(cout),
.pg(pg),
.gg(gg)
);
initial begin
// Initialize Inputs
a = 0;
b = 0;
cin = 0;
// Wait 100 nano seconds  for global rst to finish
#100;
a = 1;
b = 0;
cin = 1;
// Wait 100 nano seconds  for global rst to finish
#100;
a = 2;
b = 2;
cin = 0;
// Wait 100 nano seconds  for global rst to finish
#100;
a = 3;
b = 2;
cin = 1;
// Wait 100 nano seconds  for global rst to finish
#100;
a = 6;
b = 3;
cin = 0;
// Wait 100 nano seconds  for global rst to finish
#100;
a = 1;
b = 6;
cin = 0;
// Wait 100 nano seconds  for global rst to finish
#100;
// Add stimulus here
end
endmodule