D- Flip Flop Verilog HDL

A D-  Flipflop is the simplest example of a sequential machine. Verilog HDL describes 2-positive edge D- flip-flops in two different modules. The first responds only to the clock signal Clk, the second includes an asynchronous signal reset input rst. Output Q must be declared as a register reg data type in
addition to being listed as an output. Because in a procedural assignment statement, it is a target output. The keyword posedge endures that the transfer of input D into Q is synchronized by the positive-edge transition of Clk. A change in D input at any other time does not change in Output Q.

Positive and Negative Edge D flipflop

The 2nd module includes an Asynchronous reset input, in addition to the synchronous

clk. A specific form of an if statement is used to describe such a flip-flop so that the model

can be synthesized by a software tool. The event expression in the always statement after the @ symbol may have any number of edge events, either posedge or negedge. For modelling hardware,

one event must be a clock event. The other events specify conditions under

which asynchronous logic is to be executed. The flip flop designer knows which signal is the clock signal, but the clock is not an identifier that software tools automatically recognize, as the synchronizing signal of a flip flop circuit. The software tool must be able to conclude which signal is the clock signal, so you need to write the description in a way that enables the software tool to conclude the clock signal correctly, The rules are simple to follow:

( 1) Each if or else if statement in the procedural assignment statements is to correspond to an asynchronous event, (2) the last else statement cornponds to the clock event, and (3) the

asynchronous events are tested first. Thm am two edge events in the second duk of HDL D flip-flop. The negedge rst (reset) event is asynchronous, since it matches the if (-rst) statement. As long as reset signal rst is 0, output Q is cleared to 0. If Clock signal Clk has a positive transition, its effect is

blocked only if reset signal rst is logic 1 can the posedge clock event synchrounously transfer Input D into Output Q.

D- Positive edge triggered flip-flop

Master-Slave D flip-flop

fpga verilog code example

HDL Verilog of D flipflop
// D flip-flop without reset
module D-Flip (Q, D, Clk);
output Q;
input D, Clk;
reg Q;
always @ (posedge Clk)
Q <= D;
endmodule

// D flipflop with asynchronous reset

module DFlip (output reg Q, input D, Clk, rst);
always @ (posedge Clk, negedge rst)
If (-rst) Q <= I'b0;          // Same as: if (rst == 0)
else Q <= D;
endmodule