Ripple Counter

Verilog HDL for Ripple Counter:

Here is an example of Verilog code for a ripple counter, which is a type of counter that uses a single clock input to increment the count value: 

fpga verilog code example

Example#1

module ripple_counter(input clk, input rst, output reg [3:0] count);

always @(posedge clk) begin

    if (rst)

        count <= 4'b0000;

    else

        count <= count + 1'b1;

end

endmodule

This code defines a module called "ripple_counter" that has a 4-bit output (count) and two inputs: a clock input (clk) and a reset input (rst). The always block is triggered on the rising edge of the clock input and increments the count value by 1 on each rising edge of the clock. The if-else statement checks the reset input, if it is high the count is reset to zero.

The output will be the count value of the ripple counter. The count value will increment every clock cycle until it reach the maximum value of the count register. It's important to note that ripple counters are not recommended for high-frequency or high-speed applications as the propagation delay of the output stage causes the output to change at different times for each bit, resulting in glitches and inaccuracies.

Example# 2

!timescale 1ns/100 ps
module Ripple-Counter_4bit (A3, A2, Al, A0, Count, Reset);
output  A3, A2, Al, A0;
input    Count, R~set;
// Instantiate complementing flip-flop
Comp_D_flip_flop F0 (A0, Count, Reset);
Comp_D_flip_flop Fl (A1, A0, Reset);
Comp_D_flip_flop F2 (A2, A1 , Reset);
Comp_D_flip_flop F3 (A3, A2, Reset);
endmodule
// Complementing flip-flop with delay
// lnput to D flip-flop = Q'
module Comp_D_flip_flop (Q, CLK, Reset);
output   Q;
Input    CLK, Reset;
reg        Q;
always @  (negedge CLK, posedge Reset)
If (Reset) Q <= 1 'b0;
else Q <= #2 ~Q;                       //Intra-assignment delay
endmodule
// Stimulus for testing ripple counter
module t_Ripple_Counter_4bit;
reg Count;
reg Reset;
wire A0, Al , A2 A3;
// Instantiate ripple oounter
Rippte_Counter_4bit M0 (A3, A2, At, A0, Count, Reset);
always
#5 Count = ~Count;
lnitial
    begin
       Count = 1'b0;
       Reset = l'bl;
      #4 Reset = l'b0;
end
initial#170 $finish;

endmodule